1. Technical Field
The disclosure relates in general to a semiconductor device and a logic array structure thereof, and more particularly to a 3D semiconductor device and a 3D logic array structure thereof.
2. Description of the Related Art
In the manufacturing of high density memory devices, the amount of data per unit area on an integrated circuit can be a critical factor. Thus, as the critical dimensions of the memory devices approach technology limits, techniques for stacking multiple levels of memory cells have been proposed in order to achieve greater storage density and lower costs per bit. Also, new memory technologies are being deployed, including phase change memory, ferromagnetic memory, metal oxide based memory and so on.
The memory technologies being deployed can require a different sequence of manufacturing steps, than do the supporting peripheral circuits such as the logic for address decoders, state machines, and command decoders. As a result of the need to support the manufacturing steps for both the memory array and the peripheral circuits, the manufacturing lines needed to implement memory devices can be more expensive, or compromises are made in the type of circuitry implemented in the peripheral circuits. This leads to higher costs for integrated circuits made using more advanced technologies.
As costs for manufacturing higher and higher memory capacity in integrated circuit memory devices continues to increase, it is desirable to provide an integrated circuit memory structure having a lower manufacturing costs.